LM98640QML-SP Datasheet, PDF (27/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

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LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
Feature Description (continued)
7.3.2.2 CDS Mode Biasing
Correlated Double Sampling mode does not require as precise a DC bias point as does Sample and Hold mode.
This is due mainly to the nature of CDS itself, that is, the Video Signal voltage is referenced to the Reset Level
voltage instead of the static DC VCLP voltage. The common mode voltage of these two points on the CCD
waveform have little bearing on the resulting differential result. However, the DC bias point does need to be
established to ensure the CCD waveform’s common mode voltage is within rated operating ranges.
OS_X-
SAMPLE
C_PAR
CLAMP
C_S
HOLD
C_PAR
C_S
Figure 21. CDS Mode Simplified Input Diagram
The CDS mode biasing can be performed in the same way as described in the Sample and Hold Mode Biasing
section, or, an external resistor divider can be placed across the OS_X- input to provide the DC bias voltage. In
CDS Mode the OS_X+ pins should each be decoupled with 0.1µF capacitors to ground.
SAMPLE
OS_X-
I_BIAS
C_PAR
CLAMP
C_S
HOLD
C_PAR
C_S
Figure 22. CDS Mode Input Bias Current
Unlike in Sample and Hold Mode, the input bias current in CDS Mode is relatively small. Due to the architecture
of CDS switching, the average charge loss or gain on the input node is ideally zero over the duration of a pixel.
This results in a much lower input bias current, whose main source is parasitic impedances and leakage
currents. As a result of the lower input bias current in CDS Mode, maintaining the DC Bias point the input node
over the length of a line will require a much smaller AC input coupling capacitor.
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