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LM98640QML-SP Datasheet, PDF (45/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output
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ADDRESS
(BINARY)
11 1001
11 1100
11 1101
11 1110
LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
Table 9. Register Definitions - Digital Configuration (continued)
REGISTER
TITLE
Test Pattern Value
Digital Configuration
BASELINE
(BINARY)
0000 0000
0000 0000
BIT(s)
DESCRIPTION
[7:0] Lower 6 bits of Test Pattern Value Register. Specifies the lower 6 bits
of the test code value during Fixed Pattern and LVDS test, initial value
during H Gradient & V Gradient pattern, and higher value in the Lattice
and Stripe Pattern.
[7:0] Serial Communication Configuration Register.
[7:1] Not Used.
[0] Micro-Wire Automatic Read Disable.
0 Read data is always sent out on SDO during the first 8 SCLK cycles.
The register is selected by the register address in the previous cycle.
(read or write)
Test & Scan Control
0000 0000
1 Automatic read is disabled.
To read from a register two cycles need to be initiated by the master,
first cycle should be a read with the correct register address and
second can be a dummy read or read from another address or a write
cycle, and the data is sent first 8 SCLK of the second cycle. After a
write command SDO remains in Tri-State during first 8 SCLK.
[7:0] Test & Scan Control Register
[7:6] Not Used.
[5] Test Pattern Voting Switch.
0 Enable. Circuit Redundancy Voting is active.
1 Disable. First redundancy block output is used.
[4] Micro-wire Voting Switch.
0 Enable. Circuit Redundancy Voting is active.
1 Disable. First Micro-wire block output is used.
[3] Not Used.
[2] Test Reset. Resets the test block when High, normal test block function
when Low. This bit is not self-clearing.
[1] Test Mode Enable.
0 Disable.
1 Enable. Needed to run Test Pattern functions.
Device ID
0100 1000
[0] Not Used.
[7:0] Device Revision ID. Engineering samples might be x01 or x47.
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