LM98640QML-SP Datasheet, PDF (11/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

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LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
LM98640QML Electrical Characteristics⁽¹⁾⁽²⁾ (continued)
The following specifications apply for VDD33 = 3.3V, VDD18 = 1.8V, C_L = 10pF, and f_INCLK = 40MHz unless otherwise
specified.
PARAMETER
TEST CONDITIONS
NOTES
SUB-
GROUPS
MIN TYP⁽³⁾ MAX UNIT
PSRR
Dynamic Power Supply Rejection
Ratio
CDS Gain = 1x
PGA Gain = 1x
200 mVpp, 200 KHz
200 mVpp, 500 KHz
200 mVpp, 1 MHz
200 mVpp, 1.5 MHz
200 mVpp, 2 MHz
See ⁽⁴⁾
-72.3
-72
-71
dB
-68
-66
INTERNAL REFERENCE SPECIFICATIONS
V_REFBG
Reference Voltage
Reference Tolerance
(chip to chip)
R_REFBG
Reference Impedance
V_REFTC
Temperature Coefficient
25°C to 125°C
-55°C to 25°C
See ⁽⁵⁾
See ⁽⁵⁾
See ⁽⁵⁾
1.218
±2
20
80
50
V
%
kΩ
ppm/
°C
INPUT SAMPLING CIRCUIT SPECIFICATIONS
CDS Gain=1x, PGA Gain=1x
1, 2, 3
2
V_IN
Input Voltage Level
CDS Gain=2x, PGA Gain=1x
CDS Gain=1x, PGA Gain=0.7x
1 Vp-p
2.85
V_RESET
I_{IN_SH}
C_SH
I_{IN_CDS}
R_CLPIN
Reset Feed Through
CDS Gain = 1x
Sample and Hold Mode
Input Leakage Current
OS_X = VDD33 (OS_X = VSS)
CDS Gain = 2x
Sample/Hold Mode
Equivalent Input Capacitance
OS_X = VDD33 (OS_X = VSS)
CDS Gain = 1x
(see Figure 20)
CDS Gain = 2x
CDS Mode
Input Leakage Current
OS_X = VDD33 (OS_X = VSS)
CLPIN Switch Resistance
(OS_X to VCLP Node in Figure 17)
See ⁽⁵⁾
See ⁽⁵⁾
See ⁽⁵⁾
See ⁽⁵⁾
See ⁽⁵⁾
See ⁽⁵⁾
500
mV
384
μA
-475
µA
4
pF
8
pF
300
nA
16
Ω
(4) Dynamic Power Supply Rejection Ratio is performed by injecting a 200mVpp sine wave ac coupled to the analog supply pin. The
LM98640's inputs are left floating in CDS mode and an FFT is captured. The spur ensured by the injected signal is recorded.
(5) This Parameter is ensured by design and/or characterization and is not tested.
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