LM98640QML-SP Datasheet, PDF (25/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

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Feature Description (continued)
OS_X-
LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
SAMPLE
C_S
CLAMP
CLPIN
VCLP
OS_X+
CLPIN Gating Enable
Main Configuration, Bit[3]
VCLP
DAC
5
VCLP Control, bits[4:0]
CLAMP
Sampling Mode Select
(CDS or Sample/Hold Mode)
Main Configuration, Bit[0]
Pixel rate switches to sample OS signal and reference voltages.
Optional line rate switch to clamp OS input to VCLP node.
Static switches controlled by Configuration Registers
SAMPLE, CLAMP, and HOLD are internally generated timing signals.
Figure 17. Input Structure Diagram
HOLD
C_S
SH
Dummy Pixels
Optical Black Pixels
Invalid
Pixels
Valid Pixels
OSX
CLPIN
CLAMP
CLPIN_GATED
Figure 18. Typical CCD Waveform and LM98640QML Input Clamp Signal (CLPIN)
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