LM98640QML-SP Datasheet, PDF (43/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

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ADDRESS
(BINARY)
10 0000
10 0001
10 0010
10 0011
10 0101
10 1000
LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
Table 8. Register Definitions - Timing Configuration
REGISTER
TITLE
Clamp Start
BASELINE
(BINARY)
0000 1000
BIT(s)
[7:0] Clamp Start Register.
DESCRIPTION
[7:6] Not Used.
Clamp End
0001 1100
[5:0] CLAMP Starting Index. 0-63d position for rising edge of CLAMP signal.
Valid only in CDS Mode.
[7:0] Clamp End Register.
[7:6] Not Used.
Sample Start
0010 1000
[5:0] CLAMP End Index. 0-63d position for falling edge of CLAMP signal.
Valid only in CDS Mode.
[7:0] Sample Start Register.
[7:6] Not Used.
Sample End
0011 1100
[5:0] SAMPLE starting Index. 0-63d position for rising edge of SAMPLE
signal.
[7:0] Sample End Register.
[7:6] Not Used.
INCLK Range
0000 0010
[5:0] SAMPLE End Index. 0-63d position for falling edge of SAMPLE signal.
[7:0] INCLK Range Register.
[7] Not Used.
[6:4] INCLK Range.
000 25 to 40 MHz Operation
001 14 to 25 MHz Operation
010 10 to 14 MHz Operation
011 7.5 to 10 MHz Operation
100 6 to 7.5 MHz Operation
101 5 to 6 MHz Operation
110 Not Used
111 Not Used
[3:2] Not Used.
DLL Configuration
0000 1111
[1:0] DLL Range
11 Reserved
10 14 to 40 MHz Operation
01 7.5 to 14 MHz Operation
00 5 to 7.5 MHz Operation
[7:0] DLL Configuration Register
[7:1] Reserved
[0] DLL Reset. (Self Clearing)
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