LM98640QML-SP Datasheet, PDF (40/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
www.ti.com
ADDRESS
(BINARY)
00 0011
00 0100
00 0101
Table 6. Register Definitions - Analog Configuration (continued)
REGISTER
TITLE
ADC Power Trimming
BASELINE
(BINARY)
0101 1011
BIT(s)
DESCRIPTION
[7:0] ADC Power Trimming Register.
[7:6] Reserved. Set to 2'b01.
[5:3] ADC Current Trimming 2(Not Binary Weighted)
000 25% Power
001 50% Power
011 75% Power (Default)
111 100% Power
VCLP Control
0111 0100
[2:0] ADC Current Trimming 1 (Not Binary Weighted)
000 25% Power
001 50% Power
011 75% Power (Default)
111 100% Power
[7:0] Voltage Clamp Buffer Control Register.
[7] Not Used
[6] Buffer Enable
0 Disabled. Resistor Ladder is driving VCLP pin.
1 Enabled. Resistor Ladder is buffered to VCLP pin.
[5] VCLP Enable
0 Disabled. VCLP pin can be externally driven.
1 Enabled. VCLP pin is in output mode.
LVDS Output Modes
0000 1110
[4:0] Voltage Level of VCLP pin.
VCLP range is 200mV to 3.1V in 100mV steps for (binary) settings
00000 to 11101. Settings 11110 and 11111 are not used.
[7:0] LVDS Output Configuration Register.
[7] Serializer Data Reset. (Not self-clearing)
[6:4] Not Used.
[3] LVDS Output Mode
0 Dual Lane Mode (see Output Mode 1 - Dual Lane)
1 Quad Lane Mode (see Output Mode 2 - Quad Lane)
[2] LVDS Driver Enable.
0 LVDS Drivers Disabled
1 LVDS Drivers Enabled
(Note: In Dual Lane Mode TX0 and TX3 are disabled regardless of
driver enable)
[1:0] LVDS Amplitude and Common Mode Voltage.
00 250mV (1.2V DC Offset)
01 300mV (1.2V DC Offset)
10 350mV (1.1V DC Offset)
11 400mV (1.1V DC Offset)
40
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LM98640QML-SP