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| LM98640QML-SP Datasheet, PDF (31/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output | |||
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www.ti.com
LM98640QML-SP
SNAS461D â MAY 2010 â REVISED SEPTEMBER 2015
INCLK
TXFRM
tDOD
Odd Output
Tag
Even Output
Tag
TXOUT1
(CH1 Data)
DB DB DB DB DB DB DB DB DB DB DB DB DB DB
13 12 11 10 9
8
7
6
5
4
3
2
1
0
DB DB DB DB DB DB DB
13 12 11 10 9
8
7
TXOUT2
(CH2 Data)
TXCLK
DB DB DB DB DB DB DB DB DB DB DB DB DB DB
13 12 11 10 9
8
7
6
5
4
3
2
1
0
tDSO
tDSE
DB DB DB DB DB DB DB
13 12 11 10 9
8
7
TXOUT0 and TXOUT3 pairs at high
impedance.
Figure 24. Dual Lane LVDS Output Timing Diagram
7.3.6.3.2 Output Mode 2 - Quad Lane
In Quad Lane mode each input channel is split into two data lanes which are presented at 8X the pixel rate. The
MSBs (bits 13 through 7) will be presented to one channel while the LSBs (bits 6 through 0) will be presented to
the other. A frame signal is run at the pixel clock rate with the rising edge coincident with the transition of the
MSB of the data and the falling edge coincident with the transition of bits 10 and 3 of the data lanes for an odd
output value, and coincident with the transition of bits 11 and 4 for a even output value. A differential clock is also
output with rising edge transitions aligned within each data eye. Data rates for Quad Lane mode range from
40Mbps, with a 5MHz clock, up to 320Mbps, with a 40MHz clock.
INCLK
tDOD
Odd Output
Tag
Even Output
Tag
TXFRM
TXOUT1
(CH1 MSB)
TXOUT0
(CH1 LSB)
TXOUT2
(CH2 MSB)
TXOUT3
(CH2 LSB)
TXCLK
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
tQSR
DB5
DB4
tQHF
DB3
DB2
DB1
DB0
DB13
DB12
DB11
DB6
DB5
DB4
DB13
DB12
DB11
DB6
DB5
DB4
Figure 25. Quad Lane LVDS Data Output Timing Diagram
Copyright © 2010â2015, Texas Instruments Incorporated
Product Folder Links: LM98640QML-SP
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