SMJ320VC5416 Datasheet, PDF (83/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
Table 5–31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)^†
5416-100
MASTER
SLAVE
UNIT
MIN MAX
MIN MAX
tsu(BDRV-BCKXL) Setup time, BDR valid before BCLKX low
th(BCKXL-BDRV) Hold time, BDR valid after BCLKX low
12
2 – 6P*^‡
ns
4
5 + 12P*^‡
ns
* Not production tested.
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1 / (2 * processor clock)}
Table 5–32. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)^†
PARAMETER
5416-100
MASTER^§
SLAVE
UNIT
MIN MAX
MIN
MAX
th(BCKXH-BFXL)
td(BFXL-BCKXL)
td(BCKXH-BDXV)
Hold time, BFSX low after BCLKX high^¶
Delay time, BFSX low to BCLKX low#
Delay time, BCLKX high to BDX valid
D – 3* D + 4
ns
T – 4* T + 3*
ns
– 4*
5 6P + 2*^‡ 10P + 17^‡ ns
tdis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX high
– 2*
4* 6P – 4*^‡ 10P + 17*^‡ ns
td(BFXL-BDXV)
Delay time, BFSX low to BDX valid
C – 2* C + 4* 4P + 2*^‡ 8P + 17*^‡ ns
* Not production tested.
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1 / (2 * processor clock)}
§ _{T = BCLKX period = (1 + CLKGDV) * 2P}
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶ _{FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX}
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(BCLKX).
BCLKX
LSB
BFSX
tdis(BCKXH-BDXHZ)
BDX
Bit 0
BDR
Bit 0
th(BCKXH-BFXL)
td(BFXL-BDXV)
tsu(BDRV-BCKXL)
MSB
td(BFXL-BCKXL)
Bit(n-1)
Bit(n-1)
td(BCKXH-BDXV)
(n-2)
(n-3)
th(BCKXL-BDRV)
(n-2)
(n-3)
(n-4)
(n-4)
Figure 5–27. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
April 2003 – Revised July 2003
SGUS035A
73