SMJ320VC5416 Datasheet, PDF (25/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
BIT
NO.
NAME
15–7
IPTR
6
MP/MC
5
OVLY
4
AVIS
3
DROM
2
CLKOFF
1
SMUL
0
SST
Table 3–2. Processor Mode Status (PMST) Register Bit Fields
RESET
VALUE
FUNCTION
1FFh
Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt
vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these
bits are all set to 1; the reset vector always resides at address FF80h in program memory space. The
RESET instruction does not affect this field.
Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip ROM to be addressable in
program memory space.
MP/MC
pin
- MP/MC = 0: The on-chip ROM is enabled and addressable.
- MP/MC = 1: The on-chip ROM is not available.
MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset. This
pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can
also be set or cleared by software.
RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space.
The values for the OVLY bit are:
0 - OVLY = 0: The on-chip RAM is addressable in data space but not in program space.
- OVLY = 1: The on-chip RAM is mapped into program space and data space. Data page 0 (addresses
0h to 7Fh), however, is not mapped into program space.
Address visibility mode. AVIS enables/disables the internal program address to be visible at the
address pins.
- AVIS = 0: The external address lines do not change with the internal program address. Control and
0
data lines are not affected and the address bus is driven with the last address on the bus.
- AVIS = 1: This mode allows the internal program address to appear at the pins of the 5416 so that
the internal program address can be traced. Also, it allows the interrupt vector to be decoded in
conjunction with IACK when the interrupt vectors reside on on-chip memory.
DROM enables on-chip DARAM4–7 to be mapped into data space. The DROM bit values are:
0 - DROM = 0: The on-chip DARAM4–7 is not mapped into data space.
- DROM = 1: The on-chip DARAM4–7 is mapped into data space.
0
CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high
level.
Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before
N/A performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1
and FRCT = 1.
N/A
Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before
storing in memory. The saturation is performed after the shift operation.
3.6 On-Chip Peripherals
The 5416 device has the following peripherals:
• Software-programmable wait-state generator
• Programmable bank-switching
• A host-port interface (HPI8/16)
• Three multichannel buffered serial ports (McBSPs)
• A hardware timer
• A clock generator with a multiple phase-locked loop (PLL)
• Enhanced external parallel interface (XIO2)
• A DMA controller (DMA)
April 2003 – Revised July 2003
SGUS035A
15