SMJ320VC5416 Datasheet, PDF (33/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
15
10
9
8
7
6
5
4
2
1
0
Reserved
XMCME
XPBBLK
XPABLK
XCBLK
XMCM
R
R/W
R/W
R/W
R
R/W
15
10
9
8
7
6
5
4
2
1
0
Reserved
RMCME
RPBBLK
RPABLK
RCBLK
Resvd RMCM
R
R/W
R/W
R/W
R
R
R/W
LEGEND: R = Read, W = Write
Figure 3–10. Multichannel Control Registers (MCR1 and MCR2)
The 5416 McBSP has two working modes:
• In the first mode, when (R/X)MCME = 0, it is comparable with the McBSPs used in the 5410 where the
normal 32-channel selection is enabled (default).
• In the second mode, when (R/X)MCME = 1, it has 128-channel selection capability. Multichannel control
register Bit 9, (R/X)MCME, is used as the 128-channel selection enable bit. Once (R/X)MCME = 1, twelve
new registers ((R/X)CERC – (R/X)CERH) are used to enable the 128-channel selection.
The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface protocol.
Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported by
the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured
to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave.
Although the BCLKS pin is not available on the 5416 HFG package, the 5416 is capable of synchronization
to external clock sources. BCLKX or BCLKR can be used by the sample rate generator for external
synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the PCR to
accommodate this option.
15
14
Reserved
RW
13
XIOEN
RW
12
RIOEN
RW
11
FSXM
RW
10
FSRM
RW
9
CLKXM
RW
8
CLKRM
RW
7
6
SCLKME
CLKS STAT
RW
RW
Legend: R = Read, W = Write
5
DX STAT
RW
4
DR STAT
RW
3
FSXP
RW
2
FSRP
RW
Figure 3–11. Pin Control Register (PCR)
1
CLKXP
RW
0
CLKRP
RW
The selection of sample rate input clock is made by the combination of the CLKSM (bit 13 in SRGR2) bit value
and the SCLKME bit value as shown in Table 3–7.
Table 3–7. Sample Rate Input Clock Selection
SCLKME
0
0
CLKSM
0
1
SAMPLE RATE CLOCK MODE
Reserved (CLKS pin unavailable)
CPU clock
1
0
BCLKR
1
1
BCLKX
April 2003 – Revised July 2003
SGUS035A
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