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SMJ320VC5416 Datasheet, PDF (48/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor
Functional Overview
3.16 McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. The McBSP subbank address register (SPSA) is used as a pointer to select a particular register within
the subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected register.
Table 3–16 shows the McBSP control registers and their corresponding subaddresses.
Table 3–16. McBSP Control Registers and Subaddresses
McBSP0
NAME ADDRESS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPCR10
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SPCR20
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCR10
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCR20
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCR10
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCR20
39h
SRGR10
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SRGR20
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MCR10
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MCR20
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCERA0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCERB0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCERA0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCERB0
39h
PCR0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCERC0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCERD0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCERC0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCERD0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCERE0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCERF0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCERE0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCERF0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCERG0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RCERH0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCERG0
39h
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ XCERH0
39h
McBSP1
NAME ADDRESS
SPCR11
49h
SPCR21
49h
RCR11
49h
RCR21
49h
XCR11
49h
XCR21
49h
SRGR11
49h
SRGR21
49h
MCR11
49h
MCR21
49h
RCERA1
49h
RCERB1
49h
XCERA1
49h
XCERB1
49h
PCR1
49h
RCERC1
49h
RCERD1
49h
XCERC1
49h
XCERD1
49h
RCERE1
49h
RCERF1
49h
XCERE1
49h
XCERF1
49h
RCERG1
49h
RCERH1
49h
XCERG1
49h
XCERH1
49h
McBSP2
NAME ADDRESS
SPCR12
35h
SPCR22
35h
RCR12
35h
RCR22
35h
XCR12
35h
XCR22
35h
SRGR12
35h
SRGR22
35h
MCR12
35h
MCR22
35h
RCERA2
35h
RCERA2
35h
XCERA2
35h
XCERA2
35h
PCR2
35h
RCERC2
35h
RCERD2
35h
XCERC2
35h
XCERD2
35h
RCERE2
35h
RCERF2
35h
XCERE2
35h
XCERF2
35h
RCERG2
35h
RCERH2
35h
XCERG2
35h
XCERH2
35h
SUB-
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
DESCRIPTION
Serial port control register 1
Serial port control register 2
Receive control register 1
Receive control register 2
Transmit control register 1
Transmit control register 2
Sample rate generator register 1
Sample rate generator register 2
Multichannel register 1
Multichannel register 2
Receive channel enable register partition A
Receive channel enable register partition B
Transmit channel enable register partition A
Transmit channel enable register partition B
Pin control register
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
38 SGUS035A
April 2003 – Revised July 2003