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SMJ320VC5416 Datasheet, PDF (65/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor | |||
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Electrical Specifications
5.9 Ready Timing for Externally Generated Wait States
Table 5â14 and Table 5â15 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5â10, Figure 5â11, Figure 5â12, and Figure 5â13).
Table 5â14. Ready Timing Requirements for Externally Generated Wait Statesâ
5416-100
MIN
MAX
UNIT
tsu(RDY)
Setup time, READY before CLKOUT low
7
ns
th(RDY)
tv(RDY)MSTRB
th(RDY)MSTRB
tv(RDY)IOSTRB
th(RDY)IOSTRB
Hold time, READY after CLKOUT low
Valid time, READY after MSTRB lowâ¡
Hold time, READY after MSTRB lowâ¡
Valid time, READY after IOSTRB lowâ¡
Hold time, READY after IOSTRB lowâ¡
0
ns
4H â 6.2* ns
4H*
ns
4H â 6* ns
4H*
ns
* Not production tested.
â The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
â¡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
Table 5â15. Ready Switching Characteristics for Externally Generated Wait Statesâ
PARAMETER
5416-100
MIN MAX
UNIT
td(MSCL)
Delay time, CLKOUT low to MSC low
â1*
4 ns
td(MSCH)
Delay time, CLKOUT low to MSC high
â1*
4 ns
* Not production tested.
â The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
April 2003 â Revised July 2003
SGUS035A
55
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