SMJ320VC5416 Datasheet, PDF (66/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
CLKOUT
A[22:0]
D[15:0]
READY
MSTRB
MSC
tsu(RDY)
th(RDY)
tv(RDY)MSTRB
th(RDY)MSTRB
td(MSCL)
td(MSCH)
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5–10. Memory Read With Externally Generated Wait States
56 SGUS035A
April 2003 – Revised July 2003