SMJ320VC5416 Datasheet, PDF(49/92 Page) Texas Instruments – Fixed-Point Digital Signal Processor

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SMJ320VC5416 Datasheet, PDF (49/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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Functional Overview

3.17 DMA Subbank Addressed Registers

The direct memory access (DMA) controller has several control registers associated with it. The main control

the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single

memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular

with autoincrement (DMSDI) is used to access (read or write) the selected register.

When the DMSDI register is used to access the subbank, the subbank address is automatically

postincremented so that a subsequent access affects the next register within the subbank. This autoincrement

feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature

is not required, the DMSDN register should be used to access the subbank. Table 3â17 shows the DMA

controller subbank addressed registers and their corresponding subaddresses.

Table 3â17. DMA Subbank Addressed Registers

NAME

ÃÃÃÃÃ DMSRC0

ÃÃÃÃÃ DMDST0

ÃÃÃÃÃ DMCTR0

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMSFC0

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMMCR0

DMSRC1

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMDST1

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMCTR1

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMSFC1

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMMCR1

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMSRC2

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMDST2

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMCTR2

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMSFC2

DMMCR2

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMSRC3

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMDST3

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMCTR3

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMSFC3

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMMCR3

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMSRC4

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMDST4

DMCTR4

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMSFC4

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMMCR4

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMSRC5

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMDST5

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMCTR5

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMSFC5

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMMCR5

ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMSRCP

ADDRESS

56h/57h

SUB-

ADDRESS

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

DESCRIPTION

DMA channel 0 source address register

DMA channel 0 destination address register

DMA channel 0 element count register

DMA channel 0 sync select and frame count register

DMA channel 0 transfer mode control register

DMA channel 1 source address register

DMA channel 1 destination address register

DMA channel 1 element count register

DMA channel 1 sync select and frame count register

DMA channel 1 transfer mode control register

DMA channel 2 source address register

DMA channel 2 destination address register

DMA channel 2 element count register

DMA channel 2 sync select and frame count register

DMA channel 2 transfer mode control register

DMA channel 3 source address register

DMA channel 3 destination address register

DMA channel 3 element count register

DMA channel 3 sync select and frame count register

DMA channel 3 transfer mode control register

DMA channel 4 source address register

DMA channel 4 destination address register

DMA channel 4 element count register

DMA channel 4 sync select and frame count register

DMA channel 4 transfer mode control register

DMA channel 5 source address register

DMA channel 5 destination address register

DMA channel 5 element count register

DMA channel 5 sync select and frame count register

DMA channel 5 transfer mode control register

DMA source program page address (common channel)

April 2003 â Revised July 2003

SGUS035A

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