SMJ320VC5416 Datasheet, PDF (70/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.10 HOLD and HOLDA Timings
Table 5–16 and Table 5–17 assume testing over recommended operating conditions and H = 0.5t_c(CO) (see
Figure 5–14).
Table 5–16. HOLD and HOLDA Timing Requirements
tw(HOLD)
tsu(HOLD)
Pulse duration, HOLD low duration
Setup time, HOLD before CLKOUT low^†
* Not production tested.
5416-100
MIN MAX
4H+8*
7
UNIT
ns
ns
tdis(CLKL-A)
tdis(CLKL-RW)
tdis(CLKL-S)
ten(CLKL-A)
ten(CLKL-RW)
ten(CLKL-S)
tv(HOLDA)
tw(HOLDA)
Table 5–17. HOLD and HOLDA Switching Characteristics
PARAMETER
Disable time, Address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, Address, PS, DS, IS valid from CLKOUT low
Enable time, R/W enabled from CLKOUT low
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
Valid time, HOLDA low after CLKOUT low
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration
5416-100
MIN MAX
3*
3*
3*
2H+3*
2H+3*
2 2H+3*
– 1*
4
– 1*
4*
2H–3*
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
* Not production tested.
† _{This input can be driven from an asynchronous source, therefore, there are no specific timing requirements with respect to CLKOUT, however,}
if this timing is met, the input will be recognized on the CLKOUT edge referenced.
60 SGUS035A
April 2003 – Revised July 2003