SMJ320VC5416 Datasheet, PDF (64/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.8.4 I/O Write
Table 5–13 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5t_c(CO) (see
Figure 5–9).
Table 5–13. I/O Write Switching Characteristics
PARAMETER
td(CLKL-A)
tsu(A)IOSL
Delay time, CLKOUT low to address valid^†
Setup time, address valid before IOSTRB low^†
td(CLKL-D)W
Delay time, CLKOUT low to write data valid
tsu(D)IOSH
Setup time, data valid before IOSTRB high
th(D)IOSH
Hold time, data valid after IOSTRB high
td(CLKL-IOSL) Delay time, CLKOUT low to IOSTRB low
tw(SL)IOS
Pulse duration, IOSTRB low
td(CLKL-IOSH) Delay time, CLKOUT low to IOSTRB high
* Not production tested.
† _{Address R/W, PS, DS, and IS timings are included in timings referenced as address.}
5416-100
MIN MAX
– 1*
4
2H – 3
– 1*
4
2H – 5 2H + 6*
2H – 5* 2H + 6*
– 1*
4
2H – 2*
– 1*
4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
A[22:0]^†
td(CLKL-A)
tsu(A)IOSL
td(CLKL-D)W
td(CLKL-A)
td(CLKL-D)W
D[15:0]
IOSTRB
td(CLKL-IOSL)
tsu(D)IOSH
td(CLKL-IOSH)
th(D)IOSH
R/W^†
tw(SL)IOS
IS^†
† _{Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.}
Figure 5–9. Parallel I/O Port Write (IOSTRB = 0)
54 SGUS035A
April 2003 – Revised July 2003