SMJ320VC5416 Datasheet, PDF (76/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.14 Multichannel Buffered Serial Port (McBSP) Timing
5.14.1 McBSP Transmit and Receive Timings
Table 5–21 and Table 5–22 assume testing over recommended operating conditions (see Figure 5–21 and
Figure 5–22).
Table 5–21. McBSP Transmit and Receive Timing Requirements^†
tc(BCKRX)
tw(BCKRX)
Cycle time, BCLKR/X^‡
Pulse duration, BCLKR/X high or BCLKR/X low^‡
tsu(BFRH-BCKRL) Setup time, external BFSR high before BCLKR low
BCLKR/X ext
BCLKR/X ext
BCLKR int
BCLKR ext
5416-100
MIN
4P^§
2P–1*^§
MAX
8
1
UNIT
ns
ns
ns
th(BCKRL-BFRH) Hold time, external BFSR high after BCLKR low
BCLKR int
1
ns
BCLKR ext
2
tsu(BDRV-BCKRL) Setup time, BDR valid before BCLKR low
BCLKR int
7
ns
BCLKR ext
1
th(BCKRL-BDRV) Hold time, BDR valid after BCLKR low
BCLKR int
2
ns
BCLKR ext
3
tsu(BFXH-BCKXL) Setup time, external BFSX high before BCLKX low
BCLKX int
8
ns
BCLKX ext
1
th(BCKXL-BFXH) Hold time, external BFSX high after BCLKX low
BCLKX int
0
ns
BCLKX ext
2
tr(BCKRX)
Rise time, BCKR/X
BCLKR/X ext
6* ns
tf(BCKRX)
Fall time, BCKR/X
BCLKR/X ext
6* ns
* Not production tested.
† _{CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.}
‡ _{Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not be achievable at}
maximum CPU clock frequency due to transmitted data timings and corresponding receive timing requirements. A separate detailed timing
analysis should be performed for each specific McBSP interface.
§ _{P = 1 / (2 * processor clock)}
66 SGUS035A
April 2003 – Revised July 2003