SMJ320VC5416 Datasheet, PDF (59/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.8 Memory and Parallel I/O Interface Timing
5.8.1 Memory Read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the
CONSEC bit in the BSCR. Table 5–8 and Table 5–9 assume testing over recommended operating conditions
with MSTRB = 0 and H = 0.5t_c(CO) (see Figure 5–5 and Figure 5–6).
Table 5–8. Memory Read Timing Requirements
ta(A)M1
ta(A)M2
Access time, read data access from address valid, first read access^†
Access time, read data access from address valid, consecutive read accesses^†
tsu(D)R
Setup time, read data valid before CLKOUT low
th(D)R
Hold time, read data valid after CLKOUT low
† _{Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.}
5416-100
MIN MAX
4H–9
2H–9
7
0
UNIT
ns
ns
ns
ns
Table 5–9. Memory Read Switching Characteristics
PARAMETER
td(CLKL-A)
Delay time, CLKOUT low to address valid^†
td(CLKL-MSL) Delay time, CLKOUT low to MSTRB low
td(CLKL-MSH) Delay time, CLKOUT low to MSTRB high
* Not production tested.
† _{Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.}
5416-100
MIN MAX
– 1*
4
– 1*
4
– 1*
4*
UNIT
ns
ns
ns
April 2003 – Revised July 2003
SGUS035A
49