SMJ320VC5416 Datasheet, PDF (74/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.12 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
Table 5–19 assumes testing over recommended operating conditions and H = 0.5t_c(CO) (see Figure 5–18).
Table 5–19. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
PARAMETER
5416-100
MIN MAX
UNIT
td(CLKL-IAQL) Delay time, CLKOUT low to IAQ low
td(CLKL-IAQH) Delay time, CLKOUT low to IAQ high
td(CLKL-IACKL) Delay time, CLKOUT low to IACK low
td(CLKL-IACKH) Delay time, CLKOUT low to IACK high
td(CLKL-A)
Delay time, CLKOUT low to address valid
tw(IAQL)
Pulse duration, IAQ low
tw(IACKL)
Pulse duration, IACK low
* Not production tested.
– 1*
– 1*
– 1.2*
– 1*
– 1*
2H – 2*
2H – 3*
4 ns
4 ns
4 ns
4 ns
4 ns
ns
ns
CLKOUT
A[22:0]
td(CLKL _{– IAQL)}
td(CLKL_–A)
td(CLKL_–A)
td(CLKL _{– IAQH)}
tw(IAQL)
IAQ
td(CLKL _{– IACKL)}
td(CLKL _{– IACKH)}
IACK
tw(IACKL)
Figure 5–18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
64 SGUS035A
April 2003 – Revised July 2003