SMJ320VC5416 Datasheet, PDF (71/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

CLKOUT
HOLD
HOLDA
A[22:0]
PS, DS, IS
D[15:0]
R/W
MSTRB
IOSTRB
tsu(HOLD)
tw(HOLD)
tsu(HOLD)
tv(HOLDA)
tv(HOLDA)
tw(HOLDA)
tdis(CLKL_–A)
tdis(CLKL_–RW)
tdis(CLKL_–S)
tdis(CLKL_–S)
Figure 5–14. HOLD and HOLDA Timings (HM = 1)
Electrical Specifications
ten(CLKL_–A)
ten(CLKL_–RW)
ten(CLKL_–S)
ten(CLKL_–S)
April 2003 – Revised July 2003
SGUS035A
61