SMJ320VC5416 Datasheet, PDF (27/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the
base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3–6 and
described in Table 3–4.
15
Reserved
R/W-0
1
0
SWSM
R/W-0
LEGEND: R = Read, W = Write
Figure 3–6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
NO.
15–1
0
Table 3–4. Software Wait-State Control Register (SWCR) Bit Fields
PIN
NAME
Reserved
SWSM
RESET
VALUE
FUNCTION
0 These bits are reserved and are unaffected by writes.
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor
of 1 or 2.
0
- SWSM = 0: wait-state base values are unchanged (multiplied by 1).
- SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.
3.6.2 Programmable Bank-Switching
Programmable bank-switching logic allows the 5416 to switch between external memory banks without
requiring external wait states for memories that need additional time to turn off. The bank-switching logic
automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or
data space.
Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at
address 0029h. The bit fields of the BSCR are shown in Figure 3–7 and are described in Table 3–5.
R = Read, W = Write
15
CONSEC
R/W-1
14
13
12
11
DIVFCT
IACKOFF
R/W-11
R/W-1
Reserved
R
2
1
0
HBH BH Res
R/W-0 R/W-0 R
Figure 3–7. Bank-Switching Control Register (BSCR) [MMR Address 0029h]
April 2003 – Revised July 2003
SGUS035A
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