SMJ320VC5416 Datasheet, PDF (62/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.8.2 Memory Write
Table 5–10 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5t_c(CO) (see
Figure 5–7).
Table 5–10. Memory Write Switching Characteristics
td(CLKL-A)
tsu(A)MSL
td(CLKL-D)W
tsu(D)MSH
th(D)MSH
td(CLKL-MSL)
tw(SL)MS
td(CLKL-MSH)
PARAMETER
Delay time, CLKOUT low to address valid^†
Setup time, address valid before MSTRB low^†
Delay time, CLKOUT low to data valid
Setup time, data valid before MSTRB high
Hold time, data valid after MSTRB high
Delay time, CLKOUT low to MSTRB low
Pulse duration, MSTRB low
Delay time, CLKOUT low to MSTRB high
5416-100
MIN
MAX
– 1*
4
2H – 3
– 1*
4
2H – 5 2H + 6
2H – 5* 2H + 6*
– 1*
4
2H – 3.2*
– 1*
4*
* Not production tested.
† _{Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.}
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
A[22:0]^†
D[15:0]
MSTRB
td(CLKL-A)
tsu(A)MSL
td(CLKL-D)W
td(CLKL-A)
tsu(D)MSH
th(D)MSH
td(CLKL-MSL)
tw(SL)MS
td(CLKL-MSH)
R/W^†
PS/DS^†
† _{Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.}
Figure 5–7. Memory Write (MSTRB = 0)
52 SGUS035A
April 2003 – Revised July 2003