SMJ320VC5416 Datasheet, PDF (72/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.11 Reset, BIO, Interrupt, and MP/MC Timings
Table 5–18 assumes testing over recommended operating conditions and H = 0.5t_c(CO) (see Figure 5–15,
Figure 5–16, and Figure 5–17).
Table 5–18. Reset, BIO, Interrupt, and MP/MC Timing Requirements
5416-100
MIN MAX
UNIT
th(RS)
th(BIO)
th(INT)
th(MPMC)
tw(RSL)
Hold time, RS after CLKOUT low#
Hold time, BIO after CLKOUT low#
Hold time, INTn, NMI, after CLKOUT low^†#
Hold time, MP/MC after CLKOUT low#
Pulse duration, RS low^‡§
2*
ns
4
ns
0
ns
4*
ns
4H+3*
ns
tw(BIO)S
Pulse duration, BIO low, synchronous
2H+3*
ns
tw(BIO)A
Pulse duration, BIO low, asynchronous
4H*
ns
tw(INTH)S
Pulse duration, INTn, NMI high (synchronous)
2H+2*
ns
tw(INTH)A
Pulse duration, INTn, NMI high (asynchronous)
4H*
ns
tw(INTL)S
Pulse duration, INTn, NMI low (synchronous)
2H+2*
ns
tw(INTL)A
Pulse duration, INTn, NMI low (asynchronous)
4H*
ns
tw(INTL)WKP
tsu(RS)
tsu(BIO)
tsu(INT)
tsu(MPMC)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
Setup time, RS before X2/CLKIN low^¶#
Setup time, BIO before CLKOUT low#
Setup time, INTn, NMI, RS before CLKOUT low#
Setup time, MP/MC before CLKOUT low#
7*
ns
3*
ns
7
ns
7
ns
5*
ns
* Not production tested.
† _{The external interrupts (INT0 – INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these inputs}
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1–0–0 sequence at the timing that is
corresponding to three CLKOUTs sampling sequence.
‡ _{If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure synchronization}
and lock-in of the PLL.
§ _{Note that RS may cause a change in clock frequency, therefore changing the value of H.}
¶ _{The diagram assumes clock mode is divide-by-2 and the CLKOUT divide factor is set to no-divide mode (DIVFCT=00 field in the BSCR).}
# _{These inputs can be driven from an asynchronous source, therefore, there are no specific timing requirements with respect to CLKOUT, however,}
if setup and hold timings are met, the input will be recognized on the CLKOUT edge referenced.
62 SGUS035A
April 2003 – Revised July 2003