SMJ320VC5416 Datasheet, PDF (77/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
Table 5–22. McBSP Transmit and Receive Switching Characteristics^†
tc(BCKRX)
tw(BCKRXH)
tw(BCKRXL)
td(BCKRH-BFRV)
PARAMETER
Cycle time, BCLKR/X#
Pulse duration, BCLKR/X high#
Pulse duration, BCLKR/X low#
Delay time, BCLKR high to internal BFSR valid
BCLKR/X int
BCLKR/X int
BCLKR/X int
BCLKR int
BCLKR ext
5416-100
MIN MAX
4P^‡
D – 1*^§ D + 1*^§
C – 1*^§ C + 1*^§
– 3*
3
0*
11
UNIT
ns
ns
ns
ns
ns
td(BCKXH-BFXV) Delay time, BCLKX high to internal BFSX valid
BCLKX int
BCLKX ext
– 1*
5
ns
3*
11
Disable time, BCLKX high to BDX high impedance following last data ^{BCLKX int}
tdis(BCKXH-BDXHZ) _{bit of transfer}
BCLKX ext
6*
ns
10*
td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid
DXENA = 0
DXENA = 1
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
– 1*^¶
3*
– 1*^¶
2.8*
10
20
ns
20
30
td(BFXH-BDXV)
Delay time, BFSX high to BDX valid
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
BFSX int
BFSX ext
–1.2*^¶
3*
7*
ns
11*
* Not production tested.
† _{CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.}
‡ _{P = 1 / (2 * processor clock)}
§ _{T = BCLKRX period = (1 + CLKGDV) * 2P}
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶ _{Minimum delay times also represent minimum output hold times.}
# _{Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not be achievable at}
maximum CPU clock frequency due to transmitted data timings and corresponding receive timing requirements. A separate detailed timing
analysis should be performed for each specific McBSP interface.
BCLKR
td(BCKRH-BFRV)
BFSR (int)
tsu(BFRH-BCKRL)
BFSR (ext)
BDR
tsu(BDRV-BCKRL)
tc(BCKRX)
tw(BCKRXH)
tw(BCKRXL)
tr(BCKRX)
td(BCKRH-BFRV)
th(BCKRL-BFRH)
Bit(n-1)
th(BCKRL-BDRV)
(n-2)
Figure 5–21. McBSP Receive Timings
tf(BCKRX)
(n-3)
April 2003 – Revised July 2003
SGUS035A
67