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SMJ320VC5416 Datasheet, PDF (50/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor | |||
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Functional Overview
Table 3â17. DMA Subbank Addressed Registers (Continued)
NAME
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMDSTP
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMIDX0
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMIDX1
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMFRI0
DMFRI1
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGSA0
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGDA0
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGCR0
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGFR0
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ XSRCDP
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ XDSTDP
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGSA1
DMGDA1
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGCR1
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGFR1
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGSA2
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGDA2
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGCR2
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGFR2
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGSA3
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGDA3
DMGCR3
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGFR3
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGSA4
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGDA4
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGCR4
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGFR4
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGSA5
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGDA5
DMGCR5
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DMGFR5
ADDRESS
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
SUB-
ADDRESS
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
DESCRIPTION
DMA destination program page address (common channel)
DMA element index address register 0
DMA element index address register 1
DMA frame index register 0
DMA frame index register 1
DMA global source address reload register, channel 0
DMA global destination address reload register, channel 0
DMA global count reload register, channel 0
DMA global frame count reload register, channel 0
DMA extended source data page (currently not supported)
DMA extended destination data page (currently not supported)
DMA global source address reload register, channel 1
DMA global destination address reload register, channel 1
DMA global count reload register, channel 1
DMA global frame count reload register, channel 1
DMA global source address reload register, channel 2
DMA global destination address reload register, channel 2
DMA global count reload register, channel 2
DMA global frame count reload register, channel 2
DMA global source address reload register, channel 3
DMA global destination address reload register, channel 3
DMA global count reload register, channel 3
DMA global frame count reload register, channel 3
DMA global source address reload register, channel 4
DMA global destination address reload register, channel 4
DMA global count reload register, channel 4
DMA global frame count reload register, channel 4
DMA global source address reload register, channel 5
DMA global destination address reload register, channel 5
DMA global count reload register, channel 5
DMA global frame count reload register, channel 5
40 SGUS035A
April 2003 â Revised July 2003
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