SMJ320VC5416 Datasheet, PDF (17/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Introduction
Table 2–2. Signal Descriptions (Continued)
TERMINAL
NAME
I/O^†
DESCRIPTION
MEMORY CONTROL SIGNALS (CONTINUED)
HOLDA
Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the
O/Z address, data, and control lines are in the high-impedance state, allowing them to be available to the external
circuitry. HOLDA also goes into the high-impedance state when OFF is low. This pin is driven high during reset.
MSC
Microstate complete. MSC indicates completion of all software wait states. When two or more software wait
states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive
O/Z high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external
wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF
is low.
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address
IAQ
O/Z _{bus and goes into the high-impedance state when OFF is low.}
TIMER SIGNALS
CLKOUT
Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as
O/Z configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the
machine-cycle rate divided by 4.
CLKMD1^‡
CLKMD2^‡
CLKMD3^‡
Clock mode select signals. CLKMD1–CLKMD3 allow the selection and configuration of different clock modes
I
such as crystal, external clock, and PLL mode. The external CLKMD1–CLKMD3 pins are sampled to determine
the desired clock generation mode while RS is low. Following reset, the clock generation mode can be
reconfigured by writing to the internal clock mode register in software.
X2/CLKIN^‡
I
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. (This is
revision-dependent, see Section 3.10 for additional information.)
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
X1
O unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision-dependent, see
Section 3.10 for additional information.)
TOUT
O/Z
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT
cycle wide. TOUT also goes into the high-impedance state when OFF is low.
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),
AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS
BCLKR0^‡
BCLKR1^‡
BCLKR2^‡
I/O/Z
Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following
reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.
BDR0
BDR1
BDR2
I
Serial data receive input
BFSR0
BFSR1
BFSR2
BCLKX0^‡
BCLKX1^‡
BCLKX2^‡
I/O/Z
Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured
as an input following reset. The BFSR pulse initiates the receive data process over BDR.
I/O/Z
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state when
OFF goes low.
BDX0
BDX1
BDX2
O/Z
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when OFF is low.
BFSX0
BFSX1
BFSX2
I/O/Z
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over
BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX goes
into the high-impedance state when OFF is low.
† _{I = Input, O = Output, Z = High-impedance, S = Supply}
‡ _{These pins have Schmitt trigger inputs.}
§ _{This pin has an internal bus holder controlled by way of the BSCR register.}
¶ _{This pin has an internal pullup resistor.}
# _{This pin has an internal pulldown resistor.}
April 2003 – Revised July 2003
SGUS035A
7