SMJ320VC5416 Datasheet, PDF (58/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.7.2 Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to
generate the internal machine cycle. The selection of the clock mode and the value of N is described in
Section 3.10. Following reset, the software PLL can be programmed for the desired multiplication factor. Refer
to the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131) for
detailed information on programming the PLL.
When an external clock source is used, the external frequency injected must conform to specifications listed
in Table 5–6.
Table 5–6 and Table 5–7 assume testing over recommended operating conditions and H = 0.5t_c(CO) (see
Figure 5–4).
tc(CI)
Table 5–6. Multiply-By-N Clock Option Timing Requirements
Cycle time, X2/CLKIN
Integer PLL multiplier N (N = 1–15)^†
PLL multiplier N = x.5^†
PLL multiplier N = x.25, x.75^†
5416-100
MIN MAX
20 200
20 100
20
50
UNIT
ns
tf(CI) Fall time, X2/CLKIN
tr(CI) Rise time, X2/CLKIN
tw(CIL) Pulse duration, X2/CLKIN low
tw(CIH) Pulse duration, X2/CLKIN high
* Not production tested.
† _{N is the multiplication factor.}
4* ns
4* ns
4*
ns
4*
ns
Table 5–7. Multiply-By-N Clock Option Switching Characteristics
PARAMETER
5416-100
MIN TYP MAX
tc(CO)
Cycle time, CLKOUT
td(CI-CO) Delay time, X2/CLKIN high/low to CLKOUT high/low
tf(CO)
Fall time, CLKOUT
tr(CO)
Rise time, CLKOUT
tw(COL) Pulse duration, CLKOUT low
tw(COH) Pulse duration, CLKOUT high
tp
Transitory phase, PLL lock-up time
* Not production tested.
10
4
H – 3*
H – 2*
7
11
2*
2*
H H + 1*
H H + 1*
30*
UNIT
ns
ns
ns
ns
ns
ns
ms
tc(CI)
tw(CIH)
tw(CIL) ^tr(CI)
tf(CI)
X2/CLKIN
CLKOUT
td(CI-CO)
tc(CO)
tp
Unstable
tw(COH)
tf(CO)
tw(COL)
tr(CO)
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5–4. Multiply-by-One Clock Timing
48 SGUS035A
April 2003 – Revised July 2003