SMJ320VC5416 Datasheet, PDF (40/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
Table 3–9 lists the DMD bit values and their corresponding destination space.
Table 3–9. DMD Section of the DMMCRn Register
DMD
DESTINATION SPACE
00
PS
01
DS
10
I/O
11
Reserved
For the CPU external access, software can configure the memory cells to reside inside or outside the program
address map. When the cells are mapped into program space, the device automatically accesses them when
their addresses are within bounds. When the address generation logic generates an address outside its
bounds, the device automatically generates an external access.
3.12.3 DMA Memory Map
The DMA memory map, shown in Figure 3–16, allows the DMA transfer to be unaffected by the status of the
MP/MC, DROM, and OVLY bits.
DLAXS = 0
SLAXS = 0
Hex
0000
005F
0060
1FFF
2000
3FFF
4000
5FFF
6000
7FFF
8000
Program
Reserved
On-Chip
DARAM0
8K Words
On-Chip
DARAM1
8K Words
On-Chip
DARAM2
8K Words
On-Chip
DARAM3
8K Words
Reserved
FFFF
Page 0
Hex
010000
Program
Reserved
017FFF
018000
019FFF
01A000
01BFFF
01C000
01DFFF
01E000
01FFFF
On-Chip
DARAM 4
8K Words
On-Chip
DARAM 5
8K Words
On-Chip
DARAM 6
8K Words
On-Chip
DARAM 7
8K Words
Page 1
Hex
0x0000
Program
Reserved
0x7FFF
0x8000
0x9FFF
0xA000
0xBFFF
0xC000
0xDFFF
0xE000
0xFFFF
On-Chip
SARAM 0/4
8K Words
On-Chip
SARAM 1/5
8K Words
On-Chip
SARAM 2/6
8K Words
On-Chip
SARAM 3/7
8K Words
Page 2 – 3
Hex
xx0000
Program
Reserved
xxFFFF
Page 4 – 127
Figure 3–16. On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0)
30 SGUS035A
April 2003 – Revised July 2003