SMJ320VC5416 Datasheet, PDF (18/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Introduction
Table 2–2. Signal Descriptions (Continued)
TERMINAL
NAME
I/O^†
DESCRIPTION
HOST-PORT INTERFACE SIGNALS
HD0–HD7^‡§
HCNTL0^¶
HCNTL1^¶
I/O/Z
I
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0–HD7 is placed in the
high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to
reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven
by the 5416, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled
at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also have Schmitt trigger inputs.
Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs
have internal pullups that are only enabled when HPIENA = 0. These pins are not used when HPI16 = 1.
HBIL^¶
I
Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup
resistor that is only enabled when HPIENA = 0. This pin is not used when HPI16 = 1.
HCS^‡¶
HDS1^‡¶
HDS2^‡¶
I
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select input
has an internal pullup resistor that is only enabled when HPIENA = 0.
I
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The strobe
inputs have internal pullup resistors that are only enabled when HPIENA = 0.
HAS^‡¶
I
Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the HPIA
register. HAS input has an internal pullup resistor that is only enabled when HPIENA = 0.
HR/W^¶
I
Read/write. HR/W controls the direction of the HPI transfer. HR/W has an internal pullup resistor that is only
enabled when HPIENA = 0.
HRDY
HINT
O/Z
Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the host
when the HPI is ready for the next transfer. This pin is driven high during reset.
O/Z
Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT
goes into the high-impedance state when OFF is low. This pin is not used when HPI16 = 1.
HPIENA#
HPI16#
HPI module select. HPIENA must be tied to DVDD to have HPI selected. If HPIENA is left open or connected to
I
ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data bus
has holders set. HPIENA is provided with an internal pulldown resistor that is always active. HPIENA is sampled
when RS goes high and is ignored until RS goes low again. This pin should never be changed while reset is high
I
HPI16 mode selection
SUPPLY PINS
CVSS
S Ground. Dedicated ground for the core CPU
CVDD
S +VDD. Dedicated power supply for the core CPU
DVSS
S Ground. Dedicated ground for I/O pins
DVDD
S +VDD. Dedicated power supply for I/O pins
† _{I = Input, O = Output, Z = High-impedance, S = Supply}
‡ _{These pins have Schmitt trigger inputs.}
§ _{This pin has an internal bus holder controlled by way of the BSCR register.}
¶ _{This pin has an internal pullup resistor.}
# _{This pin has an internal pulldown resistor.}
8
SGUS035A
April 2003 – Revised July 2003