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SMJ320VC5416 Datasheet, PDF (63/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor | |||
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Electrical Specifications
5.8.3 I/O Read
Table 5â11 and Table 5â12 assume testing over recommended operating conditions, IOSTRB = 0, and
H = 0.5tc(CO) (see Figure 5â8).
Table 5â11. I/O Read Timing Requirements
ta(A)M1
Access time, read data access from address valid, first read accessâ
tsu(D)R
Setup time, read data valid before CLKOUT low
th(D)R
Hold time, read data valid after CLKOUT low
â Address R/W, PS, DS, and IS timings are included in timings referenced as address.
5416-100
MIN MAX
4H â 9
7
0
UNIT
ns
ns
ns
Table 5â12. I/O Read Switching Characteristics
PARAMETER
td(CLKL-A)
Delay time, CLKOUT low to address validâ
td(CLKL-IOSL)
Delay time, CLKOUT low to IOSTRB low
td(CLKL-IOSH)
Delay time, CLKOUT low to IOSTRB high
* Not production tested.
â Address R/W, PS, DS, and IS timings are included in timings referenced as address.
5416-100
MIN MAX
â 1*
4
â 1*
4
â 1*
4
UNIT
ns
ns
ns
CLKOUT
A[22:0]â
D[15:0]
td(CLKL-A)
td(CLKL-IOSL)
td(CLKL-IOSH)
td(CLKL-A)
ta(A)M1
tsu(D)R
th(D)R
IOSTRB
R/Wâ
ISâ
â Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5â8. Parallel I/O Port Read (IOSTRB = 0)
April 2003 â Revised July 2003
SGUS035A
53
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