SMJ320VC5416 Datasheet, PDF (24/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
3.5.1 Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved
at each vector location to accommodate a delayed branch instruction which allows branching to the
appropriate interrupt service routine without the overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.
NOTE: The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
15
7
6
5
4
3
2
1
0
IPTR
CLK
MP/MC OVLY AVIS DROM
SMUL SST
OFF
R/W-1FF
MP/MC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Pin
LEGEND: R = Read, W = Write
Figure 3–4. Processor Mode Status (PMST) Register
14 SGUS035A
April 2003 – Revised July 2003