SMJ320VC5416 Datasheet, PDF (35/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
Table 3–8. Clock Mode Settings at Reset
CLKMD1
CLKMD2
CLKMD3
CLKMD RESET
VALUE
CLOCK MODE^†
0
0
0
0000h
1/2 (PLL disabled)
0
0
1
9007h
PLL x 10
0
1
0
4007h
PLL x 5
1
0
0
1007h
PLL x 2
1
1
0
F007h
PLL x 1
1
1
1
0000h
1/2 (PLL disabled)
1
0
1
F000h
1/4 (PLL disabled)
0
1
1
—
Reserved (Bypass mode)
† _{The external CLKMD1–CLKMD3 pins are sampled to determine the desired clock generation mode}
while RS is low. Following reset, the clock generation mode can be reconfigured by writing to the internal
clock mode register in software.
3.11 Enhanced External Parallel Interface (XIO2)
The 5416 external interface has been redesigned to include several improvements, including: simplification
of the bus sequence, more immunity to bus contention when transitioning between read and write operations,
the ability for external memory access to the DMA controller, and optimization of the power-down modes.
The bus sequence on the 5416 still maintains all of the same interface signals as on previous 54x devices,
but the signal sequence has been simplified. Most external accesses now require 3 cycles composed of a
leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide
additional immunity against bus contention when switching between read operations and write operations. To
maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous
54x devices is available.
April 2003 – Revised July 2003
SGUS035A
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