SMJ320VC5416 Datasheet, PDF (37/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
Figure 3–13 shows the bus sequence for repeated memory reads in consecutive mode. The accesses shown
in Figure 3–13 require (2 + n) CLKOUT cycles to complete, where n is the number of consecutive reads
performed.
CLKOUT
A[22:0]
D[15:0]
READ
READ
READ
R/W
MSTRB
PS/DS
Leading
Cycle
Read
Cycle
Read
Cycle
Read
Cycle
Trailing
Cycle
Figure 3–13. Consecutive Memory Read Bus Sequence (n = 3 reads)
April 2003 – Revised July 2003
SGUS035A
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