SMJ320VC5416 Datasheet, PDF (82/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
Table 5–29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)^†
5416-100
MASTER
SLAVE
UNIT
tsu(BDRV-BCKXH) Setup time, BDR valid before BCLKX high
th(BCKXH-BDRV) Hold time, BDR valid after BCLKX high
MIN MAX
MIN MAX
12
2 – 6P*^‡
ns
4
5 + 12P*^‡
ns
* Not production tested.
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1 / (2 * processor clock)}
Table 5–30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)^†
PARAMETER
th(BCKXH-BFXL)
td(BFXL-BCKXL)
td(BCKXL-BDXV)
tdis(BCKXH-BDXHZ)
Hold time, BFSX low after BCLKX high^¶
Delay time, BFSX low to BCLKX low#
Delay time, BCLKX low to BDX valid
Disable time, BDX high impedance following last data bit from
BCLKX high
5416-100
MASTER^§
SLAVE
MIN MAX
MIN
MAX
T – 3* T + 4
D – 4* D + 3*
– 4*
5 6P + 2*^‡ 10P + 17^‡
UNIT
ns
ns
ns
D – 2* D + 3*
ns
tdis(BFXH-BDXHZ)
td(BFXL-BDXV)
Disable time, BDX high impedance following last data bit from
BFSX high
Delay time, BFSX low to BDX valid
2P – 4*^‡ 6P + 17*^‡ ns
4P + 2*^‡ 8P + 17*^‡ ns
* Not production tested.
† _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
‡ _{P = 1 / (2 * processor clock)}
§ _{T = BCLKX period = (1 + CLKGDV) * 2P}
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶ _{FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX}
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(BCLKX).
BCLKX
BFSX
BDX
BDR
LSB
Bit 0
Bit 0
th(BCKXH-BFXL)
tdis(BFXH-BDXHZ)
tdis(BCKXH-BDXHZ)
tsu(BDRV-BCKXH)
MSB
td(BFXL-BCKXL)
td(BFXL-BDXV)
td(BCKXL-BDXV)
Bit(n-1)
(n-2)
(n-3)
Bit(n-1)
th(BCKXH-BDRV)
(n-2)
(n-3)
(n-4)
(n-4)
Figure 5–26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
72 SGUS035A
April 2003 – Revised July 2003