SMJ320VC5416 Datasheet, PDF (56/92 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
X1
C1
X2/CLKIN
Crystal
C2
Figure 5–2. Internal Divide-by-Two Clock Option With External Crystal
5.7 Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or
multiplied by one of several values to generate the internal machine cycle.
5.7.1 Divide-By-Two and Divide-By-Four Clock Options
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four
to generate the internal machine cycle. The selection of the clock mode is described in Section 3.10.
When an external clock source is used, the frequency injected must conform to specifications listed in
Table 5–4.
An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left unconnected.
Table 5–3 shows the configuration options for the CLKMD pins that generate the external divide-by-2 or
divide-by-4 clock option.
Table 5–3. Clock Mode Pin Settings for the Divide-By-2 and By Divide-by-4 Clock Options
CLKMD1
0
1
1
CLKMD2
0
0
1
CLKMD3
0
1
1
1/2, PLL disabled
1/4, PLL disabled
1/2, PLL disabled
CLOCK MODE
46 SGUS035A
April 2003 – Revised July 2003