PNX1502E Datasheet, PDF (96/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 2: Overview
10.1.1 software I/O
Each GPIO pin is a tri-state pin that can be individually enabled, disabled, written or
read. Pins are grouped in groups of 16 and signals within a group can be
simultaneously enabled and changed or observed. Changes can use a mask to allow
certain pins to remain unchanged.
Note that this capability is useful for low/medium speed software implemented
protocols, as well as for observing switches, driving LEDs etc. It is highly
recommended to first use the powerful GPIO pins as protocol emulators, and not just
for static switches/LEDs (for which a solution such as a PCF8574 I²C parallel I/O is
fine).
10.1.2 timestamping
The GPIO module contains 12 timestamp units, each of which can be designated to
monitor an external GPIO pin or internal system event. For a monitored event, a
timestamp unit can be set to trigger on a rising edge, falling edge or either edge.
When a trigger occurs, a precise occurrence time (31-bit timestamp value, 75 ns
resolution) is put in a register, and an interrupt is generated.
This capability is particularly valuable for precise monitoring of key audio/video events
and controlling the internal software phase-locked loops that lock to broadcast time
references. It can also be used for medium speed signal analysis.
10.1.3 event sequence monitoring and signal generation
GPIO contains 4 queue units, each capable of monitoring or generating high-speed
signals on up to 4 GPIO pins.
This capability creates a universal protocol emulator, capable of emulating many
medium speed (0 - 20 Mbit/s) protocols using software on the TM3260 media
processor. Complex protocols, such as the MemoryStick^TM protocol with 20 Mbits/s
peak rate and 800 KB/s sustained file transfer rate have been successfully
implemented on the PNX8525 GPIO module. The PNX15xx Series GPIO is similar to
the PNX8525 GPIO module.
High speed signal analysis uses one of two modes:
• event queue hardware samples 1, 2 or 4 GPIO inputs using one out of a variety of
clocks in the system, including clock inputs or clocks generated from other GPIO
pins. Samples are packed in a word and stored in a list in system memory for
software analysis.
• event queue hardware builds an in-system memory list of timestamped GPIO pin
change events, individual per monitored GPIO pin. Edge events are timestamped
with 75 ns resolution.
Signal generation uses the same 2 features, but in reverse, i.e. a sampled signal is
transmitted, or an in-memory timestamped list of change events is output over a pin.
The event sequence monitoring mechanism can be used for many functions, and is
particularly useful for interpreting Remote Control commands, as described in
Section 10.2. Signal generation is useful for RC Blaster applications.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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