PNX1502E Datasheet, PDF (86/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 2: Overview
Table 4: TM3260 Characteristics
TM3260 VLIW CPU Features
System Interface
The TM3260 runs asynchronously with respect to system DRAM, and can operate at a frequency
lower than system DRAM to save power, or higher than system DRAM to gain performance
Software
Development
Environment
The TM3260 is supported by the advanced C/C++ compiler tools available for the PNX1300 Series
family
Application Software Applications use the TSSA, Trimedia Streaming Software Architecture, allowing modular
Architecture
development of audio, video processing functions
6. MPEG Decoding
The TM3260 processes the audio, video and the stream de-multiplexing via software.
The Variable Length decoding as well as the authentication and the de-scrambling
are supported by two coprocessors.
6.1 VLD
The PNX15xx Series VLD is an MPEG-1 and MPEG-2 parser that writes to memory
a separate data structure for macro block header and coefficient information. It is
capable of sustaining an ATSC (High Definition) bitrate. It off-loads the CPU in
applications involving MPEG-2 decoding or transcoding. Low to medium bitrate VLD
decoding, as well as VLC encoding may be done by the TM3260 CPU. MPEG-2 HD
decoding by the CPU is not supported due to CPU and system limitations.
6.2 DVD De-scrambler
The DVD-CSS module is provided to allow integrated DVD playback capability.
It provides authentication and de-scrambling for DVDs. A DVD drive can be attached
to the integrated medium-bandwidth IDE controller, and provides its data either
across the IDE interface or across a multi bit serial interface to the GPIO pins. The
resulting system memory scrambled program stream is de-scrambled by invoking a
memory to memory operation on the DVD-CSS module. The ‘cleartext’ program
stream is then de-multiplexed by software on the TM3260.
More detailed Information available on (legal) request
7. Image Processing
7.1 Pixel Format
The on-chip hardware image processing modules all use the same ‘native’ pixel
formats, as shown in Table 5. This ensures that image data produced by one module
can be read by another module.
• A limited number of native pixel formats are supported by all image subsystems,
as appropriate.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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