PNX1502E Datasheet, PDF (532/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 16: Audio Input
Interrupt status bits within AI_STATUS are persistent, meaning that once the interrupt
is triggered, it will remain asserted until cleared by setting the corresponding ACK bit
in AI_CTL. Using the above example, assuming the HBE interrupt is asserted, write a
logic ‘1’ to ACK_HBE to clear the AI_STATUS.HBE bit and deactivate the interrupt to
the system.
3.10 Timestamp Events
Audio In exports event signals associated with audio capture to the central
timestamp/timer function on-chip. The central timestamp/timer function can be used
to count the number of occurrences of each event or timestamp the occurrence of the
event or both. The event will be a positive edge pulse with the duration of the event to
be greater than or equal to 160ns. The specific event exported is:
• The ai_tstamp_event event will occur when the last sample for the current DMA
buffer reaches the internal buffer. The internal buffer referred to here is present in
the adapter and not inside the Audio In block. One precise event will occur for
each of the two DMA buffers.
The occurrence of this event represents a precise, periodic time interval which can be
used by system software for audio/video synchronization.
3.11 Diagnostic Mode
This mode can be used during the diagnostic phase of system testing to verify the
correct operation of both Audio In and Audio Out units. This loopback mode internally
feeds the I2S Audio Out to the I2S Audio In. This test can be used to check the data
flow from the Audio Out buffer to the Audio In buffer.
Audio In Operation
The Audio (I2S) Input Ports Registers (Section 4. on page 16-15) describe the
function of the control and status fields of the AI unit. To ensure compatibility with
future devices, undefined bits in MMIO registers should be ignored when read and
written as 0s.
The AI unit is reset by a PNX15xx Series hardware reset, or by writing 0x80000000 to
the AI_CTL register. Upon RESET, capture is disabled (CAP_ENABLE = 0), and
buffer1 is the active buffer (BUF1_ACTIVE = 1). The CPU initiates capture by
providing two equal size empty buffers and putting their base address and size in the
BASEn and SIZE registers. Once two valid (local memory) buffers are assigned,
capture can be enabled by writing a ‘1’ to CAP_ENABLE. The AI unit now proceeds
to fill buffer 1 with input samples. Once buffer 1 fills up, BUF1_FULL is asserted, and
capture continues without interruption in buffer 2. If BUF1_INTEN is enabled, a
SOURCE 11 interrupt request is generated.
Note that the buffers must be 64-byte aligned and multiple of 64 samples in size (the
six LSBits of AI_BASE1, AI_BASE2 and AI_SIZE are always ‘0’).
The CPU is required to assign a new, empty buffer to BASE1 and perform a ACK1
before buffer 2 fills up. Capture continues in buffer 2 until it fills up. At that time,
BUF2_FULL is asserted and capture continues in the new buffer 1.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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