PNX1502E Datasheet, PDF (756/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 25: I²C Interface
When the slave address and data direction bit have been transmitted and an
acknowledgment bit has been received, a number of status codes are possible in
STA. The appropriate action to be taken for each of the status codes is detailed in
Table 5. After a repeated start condition (state 0x10), the IIC module may switch to
the master transmitter mode by loading IIC_DAT with SLA+W.
Slave Receiver Mode
Serial data and the serial clock are received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and STOP conditions are
recognized as the beginning and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave address and direction bit.
In the slave receiver mode, a number of data bytes are received from a master
transmitter. To initiate the slave receiver mode, IIC_ADDRESS must be loaded with
the 7-bit slave address to which the IIC module will respond when addressed by a
master. Also the least significant bit of IIC_ADDRESS should be set if the interface
should respond to the general call address (0x00). The IIC_CONTROL register,
should be initialized with EN and AA set and STA and STO reset in order to enter the
slave receiver mode. Setting the AA bit will enable the logic to acknowledge its own
slave address or the general call address and EN will enable the interface.
When IIC_ADDRESS and IIC_CONTROL have been initialized, the IIC module waits
until it is addressed by its own slave address, followed by the data direction bit which
must be ‘0’ (W) for the IIC module to operate in the slave receiver mode. After its own
slave address and the W bit have been received, a valid status code can be read from
IIC_DAT. This status code should be used to vector to an interrupt service routine.
The appropriate action to be taken for each of the status codes is detailed in Table 5.
The slave receiver mode may also be entered if arbitration is lost while the IIC module
is in the master mode.
If the AA bit is reset during a transfer, the IIC module will return a not acknowledge
(logic ‘1’) to SDA after the next received data byte. While AA is reset, the IIC module
does not respond to its own slave address or a general call address. However, the I²C
bus is still monitored and address recognition may be resumed at any time by setting
AA. This means that the AA bit may be used to isolate the IIC module from the I²C
bus temporarily.
Slave Transmitter Mode
The first byte is received and handled as in the slave receiver mode. However, in this
mode, the direction bit will indicate that the transfer direction is reversed. Serial data
is transmitted via SDA while the serial clock is input through SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer.
In the slave transmitter mode, a number of data bytes are transmitted to a master
receiver. Data transfer is initialized as in the slave receiver mode. When
IIC_ADDRESS and IIC_CONTROL have been initialized, the IIC module waits until it
is addressed by its own slave address followed by the data direction bit, which must
be ‘1’ (R) for the IIC module to operate in the slave transmitter mode. After its own
slave address and the R bit have been received, a valid status code can be read from
STA. This status code is used to vector to an interrupt service routine. The
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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