PNX1502E Datasheet, PDF (461/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 13: FGPO: Fast General Purpose Output
2.4 Sample (data) Size
Data size (width) per sample is set to either 8, 16, or 32-bit using
FGPO_CTL.DATA_SIZE bit field. For 8-bit samples, four samples are packed into one
32-bit word. For 16-bit samples, two samples are packed 2 into one 32-bit word.
Packed data is read from memory in full 32-bit words.
Byte order, with which the data is read from memory, is controlled by the global
PNX15xx Series endian mode. The endian state only affects 16 and 32-bit sample
sizes.
2.5 Record or Message Size
The number of samples per record is set by FGPO_REC_SIZE field. This is amount
of data that will be output after each record or message start event unless the
FGPO_CTL.VAR_LENGTH bit is set. If the FGPO_CTL.VAR_LENGTH bit is set the
length of a record or message is set by the value of the second 32-bit word read from
the header attached to the record or message.
Valid values are in the range of 2 to 2²⁴ - 1.
Remark: The FGPI has a minimum message size of 2 or 3. See FGPI Module
specification for more information.
2.6 Records or Messages Per Buffer
The number of records or messages per buffer is set by FGPO_SIZE register.
Valid values are in the range of 1 to 2²⁴ - 1.
2.7 Stride
If the number of records or messages per buffer is greater than one, the address
stride has to be programmed into the FGPO_STRIDE register.
Output starts at a new location in the current buffer on each record or message start
event. After output starts a new address is generated by adding the contents of the
FGPO_STRIDE register to the previous starting address.
Care must be taken that FGPO_STRIDE is greater than or equal to
FGPO_REC_SIZE. Add 8 if either TSTAMP_SELECT or VAR_LENGTH bits are set.
2.8 Interrupt Events
The FGPO_IR_STATUS register contains status and interrupt event status. To
generate an interrupt to the TriMedia processor the corresponding FGPO_IR_ENA bit
must be set. To clear an interrupt event (acknowledge the interrupt) a ‘1’ must be
written to the corresponding FGPO_IR_CLR bit. The FGPO_IR_SET register can be
used to generate software interrupts.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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