PNX1502E Datasheet, PDF (239/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 7: PCI-XIO Module
Table 8: Registers Description
Bit Symbol
Acces
s
Value
Description
15:8 unlock_ssid
W
0
Writing a “0xCA” to this field will unlock the “subsystem_id” and
“subsystem_vendor” registers. A writer to the subsystem_id/
subsystemvendor” register will lock the register again.
7:0 unlock_setup
W
0
Writing a “0xCA” to this field will unlock the “classcode”,
“max_latency”, “min_gnt” and “pci_setup” registers. A write to the
“pci_setup” register to lock registers again.
Offset 0x04 0040
Image of Device ID and Vendor ID
31:16 device_id
R
0x5405 PCI configuration device ID
15:0 vendor_id
R
0x1131 PCI configuration vendor ID
Offset 0x04 0044
Image of Command/Status
31:16 status
R
0x0290 PCI configuration status register
15:0 command
R/W*
0x0000
PCI configuration command register.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
Refer to configuration register 4 for details on which bits are
implemented and controllable.
Offset 0x04 0048
Image of Class Code/Revision ID
31:8 class code
R/W* 048000 PCI configuration class code.
*Write-once/Read-only
7:0 revision id
R
1
PCI configuration revision ID
Offset 0x04 004C
Image of Latency Timer/Cache Line Size
31:24 BIST
R
0
PCI configuration BIST
23:16 Header Type
R
0
PCI configuration Header Type
15:8 latency timer
R/W* 0
PCI configuration latency timer.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
7:0 cache line size
R/W* 0
PCI configuration cache line size.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
Offset 0x04 0050
Base Address 10 Image
31:21 Base Address 10
R/W* 0
PCI configuration Base address for DRAM.
This register affects the decode and routing of the bus controllers. It
should not be relied on as stable for 10 clocks after writing.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
20:4 Reserved
R
0
3
Prefetchable
R
cfg*
*Value is determined at boot time by pci_setup register.
2:0 Type
R
0
Indicates type 0 memory space (locatable anywhere in 32-bit
address space).
Offset 0x04 0054
Base Address 14 Image
31:4 Base Address 14
R/W*
1BE00000 PCI configuration Base address for MMIO.
This register affects the decode and routing of the bus controllers. It
should not be relied on as stable for 10 clocks after writing.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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