PNX1502E Datasheet, PDF (656/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
4. Application Notes
4.0.1 PNX1300 Series versus PNX15xx Series VLD
• The MPEG-2 Macroblock Header Output Format now differs in two ways: the
First Forward Motion Vector bit[1] which was unused is now the “First Macro
Block” bit, and the sixth word bits[23:16] now contain the Slice Start Code.
• The PNX1300 Series does not implement the “Parse Long” command.
• In the VLD_STATUS register, the PNX1300 Series does not implement the
following bits:
– Bit[6] RL Overflow
• In the VLD_CONTROL register, the PNX1300 Series does not implement the
following bits:
– Bit[16] Slice_strobe
– Bit[15:8] Slice_start_code
– Bit[2] DMA_input_done_mode
• In addition, the Little_Endian mode bit is on bit[1] in the PNX1300 Series; but it is
bit[0] in this module.
5. Register Descriptions
5.1 PNX1300 Series and PNX15xx Series Register Differences
The current VLD is a compatible superset of the VLD that was implemented in the
PNX1300 Series chip. Differences in the register definitions are noted in magenta
text.
The PNX15xx Series implementation removed the RL/MBH write-back DMA
channels. Differences from the current VLD implementation are noted in blue text.
The base address for the PNX15xx Series VLD module is 0x07 5000.
5.2 VLD Register Summary
Table 9: Register Summary
Offset
Symbol
0x07 5000
VLD_COMMAND
0x07 5004
VLD_SR
0x07 5008
VLD_QS
0x07 500C
VPD_PI
0x07 5010
VLD_MC_STATUS
0x07 5014
VLD_IE
0x07 5018
VLD_CTL
Description
Variable Length Decoder Command
VLD Shift Register (shadow)
Quantization Scale Code to be output by the VLD
VLD Picture Information
VLD and MC Status register
VLD Interrupt Enable
VLD Control register
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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