PNX1502E Datasheet, PDF (624/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 20: 2D Drawing Engine
Table 6: 2D Command Registers …Continued
Offset
Symbol
Description
0x04 F448 Reserved
–
0x04F5F4
Reserved for future use
0x04 F5F8 MonoPatFColor
Foreground color for mono pattern expansion, lines,
and solid fills
0x04 F5FC MonoPatBColor
Background color for mono pattern expansion, lines,
and solid fills
Table 7: 2D Real Time Drawing Registers
Offset
Symbol
Description
0x4F600 – PatRamMono
0x4F6FFC
Monochrome Pattern cache RAM
0x4F700 – PatRamColor
0x4F7FFC
Full Color Pattern cache RAM
0x4F800 EngineStatus
Status control of the engine
0x4F804 Panic Control
Reset
0x4F808 EngineConfig
Interrupt configuration
0x4F80C HostFIFOStatus
Number of entries in the host FIFO
0x4 F810 – Reserved
0x4FFF0
Reserved for future use
0x4FFF4 PowerDown
Powerdown activation
0x4FFFC DeviceID
Module ID and aperture size
0x50000 – HostData
0x5FFFC
64KB Memory space for the host
4.2 Register Tables
Table 8: Registers Description
Bit Symbol
Acces
s
Value
2D Command Registers
Offset 0x04 F400
Source Address Base
31:29 Swap[2:0]
R/W -
28:24 Reserved
Description
Specifies endian-swapping on reads from memory.
When Swap[2] is 0, swapping is determined by the global endian
setting, possibly modified by BSI[0] in EngineConfig.
When Swap[2] is 1, swapping is determined by Swap[1:0] as shown:
00=No swapping. Memory is little-endian.
01=Bytes are swapped within each 16-bit word.
10=Words are swapped within each 32-bit double word.
11=Bytes are swapped within each 32-bit double word.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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