 English |
|
|
|
|
|
|
|
| PNX1502E Datasheet, PDF (254/819 Pages) NXP Semiconductors – Connected Media Processor | |||
| |||
| ◁ |
Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 7: PCI-XIO Module
Table 8: Registers Description
Bit Symbol
Acces
s
Value
3
en_int_sig_serr
R/W 0
2
en_int_pci_r_mabort R/W 0
1
en_int_pci_r_tabort
R/W 0
0
en_int_pci_s_tabort
R/W 0
Offset 0x04 0FE8
PCI Interrupt Clear
31:27 Reserved
R
0
26 clr_pcii_wr_err
W
0
25 clr_pcii_rd_err
W
0
24 clr_xio_wr_err
W
0
23 clr_xio_rd_err
W
0
22 clr_pcir_wr_err
W
0
21 clr_pcir_rd_err
W
0
20 clr_pwrstate_chg
W
0
19 Reserved
R
0
18 clr_pci2_wr_err
W
0
17 clr_pci2_rd_err
W
0
16 clr_pci1_wr_err
W
0
15 clr_pci1_rd_err
W
0
14 clr_pci_xio_ack_done W
0
13:12 Reserved
R
0
11 clr_serr_seen
W
0
10 Reserved
R
0
9
clr_pci_err
W
0
8
clr_base10_subword W
0
7
clr_base14_subword W
0
6
clr_base18_subword W
0
5
clr_pci_mstr_parity_err W
0
4
clr_pci_parity
W
0
3
clr_sig_serr
W
0
2
clr_pci_r_mabort
W
0
1
clr_pci_r_tabort
W
0
0
clr_pci_s_tabort
W
0
Offset 0x04 0FEC
PCI Interrupt Set
31:27 Reserved
R
0
26 set_pcii_wr_err
W
0
25 set_pcii_rd_err
W
0
24 set_xio_wr_err
W
0
23 set_xio_rd_err
W
0
Description
Enable interrupt on System Error Status
Enable interrupt on PCI Received Master Abort Status
Enable interrupt on PCI Received Target Abort Status
Enable interrupt on PCI Signaled Target Abort Status
Clear PCI DTL initiator write error ï¬ag
Clear PCI DTL initiator read error ï¬ag
Clear XIO DTL target write error ï¬ag
Clear XIO DTL target read error ï¬ag
Clear mmio register DTL target write error ï¬ag
Clear mmio register DTL target read error
Clear power state change register ï¬ag
Clear PCI2 DTL target write error ï¬ag
Clear PCI2 DTL target read error ï¬ag
Clear PCI1 DTL target write error ï¬ag
Clear PCI1 DTL target read error ï¬ag
Clear pci_xio_ack done ï¬ag
Clear serr_seen ï¬ag
Clear pci_err ï¬ag
Clear Subword Attempt to Base10 Error Status
Clear Subword Attempt to Base14 Error Status
Clear Subword Attempt to Base18 Error Status
Clear PCI Master Parity Error
Clear PCI Parity Error Status
Clear System Error Status
Clear PCI Received Master Abort Status
Clear PCI Received Target Abort Status
Clear PCI Signaled Target Abort Status
Set PCI DTL initiator write error ï¬ag
Set PCI DTL initiator read error ï¬ag
Set XIO DTL target write error ï¬ag
Set XIO DTL target read error ï¬ag
12NC 9397 750 14321
Product data sheet
Rev. 2 â 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
7-42
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese