PNX1502E Datasheet, PDF (478/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 14: FGPI: Fast General Purpose Interface
1.1 FGPI Overview
Refer to Figure 1. This block diagram shows the top level connection of the FGPI
module to the MMIO and MTL Busses within the PNX15xx Series. All external FGPI
signals are registered and routed through the Input Router module before being
presented to the FPGI module. Latency buffering of data and endian conversion is
done in the MTL DTL Adapter. All FGPI register access is through the MMIO DTL
adapter.
MMIO/DCS Bus
32
32
Clock Block
MTL Bus
32
64
32
VDI Pads
32
Input Router
Figure 1: Top Level Block Diagram
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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