PNX1502E Datasheet, PDF (627/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 20: 2D Drawing Engine
When Depth is 16, PFormat[3] enables dithering the results of an alpha blend
operation. All alpha blend operations are done with 8 bits of precision for each
component. The components of the source pixels are expanded to 8 bits by
replicating the high-order bits into the low-order bits. The results of the computations
can be thought of as being in fixed point, with 3, 4, 5 or 6 bits of precision to the left of
the decimal point, depending on the component and color format. When dithering is
enabled, a 4x4 dither is applied by adding a constant fraction to each component and
truncating the results to fit in the resulting pixel. The constant fraction is taken from
the following table, based on the X and Y coordinates of the destination pixel.
Table 12: Dithering
Format
X mod 4 = 0 X mod 4 = 1
X mod 4 = 2 X mod 4 = 3
Y mod 4 = 0
7/8
3/8
1/8
5/8
Y mod 4 = 1
1/8
5/8
7/8
3/8
Y mod 4 = 2
5/8
7/8
3/8
1/8
Y mod 4 = 3
3/8
1/8
5/8
7/8
Table 13: Source Linear
Bit Symbol
Acces
s
Value
Offset 0x04 F40C
Source Linear
31:24 Reserved
23:16 Adr[22:16]
R/W -
15:8 Adr[15:8]
R/W -
7:0 Adr[7:0]
R/W -
Description
Used to load the linear source address for a BLT operation.
This register is used to load the linear source address for a BLT operation.
It must be loaded with a pixel aligned address. Note that loading the SrcXY register
actually causes this register to be loaded with the proper linear pixel address.
This register is interpreted as a byte address, except during a monochrome host to
screen bit BLT, or a 4-bit or 8-bit expand alpha BLT. In the monochrome BLT case,
Adr[4:0] specifies the first valid bit within the first DWORD transferred by the host.
Adr[4:3] specifies the correct byte and Adr[2:0] specify the correct bit. In the 4-bit
expand case, Adr[3:0] specifies the first valid nibble within the alpha data transferred
by the host. In the 8-bit expand case, Adr[2:0] specifies the first valid byte within the
alpha data transferred by the host. This register is unchanged by drawing operations.
Table 14: Destination Linear
Bit Symbol
Acces
s
Value
Offset 0x04 F410
Destination Linear
31:24 Reserved
23:16 Adr[22:16]
R/W 0
15:8 Adr[15:8]
R/W 0
7:0 Adr[7:0]
R/W 0
Description
Used to load the starting linear pixel address for a vector or the
destination linear address for a BLT operation.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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