PNX1502E Datasheet, PDF (172/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 5: The Clock Module
xtal_clk
Clock Module
qvcp_output_enable_n
tst_clk_qvcp
slice_tst_out
PLL1
BLOCKING
GPIO
note: lcd clock path
sel_clk_qvcp
clk_lcd
clk_qvcp_out
BLOCKING
qvcp_output_enable_n
qvcp_output_select
invert_clk_qvcp
clk_qvcp
Figure 17: VDO_CLK1 Block Diagram
clk_tft note: derived from the clk_lcd
output router
VDO_CLK1
xtal_clk
Clock Module
fgpo_output_enable_n
tst_clk_fgpo
slice_tst_out
PLL1
UNDEF
DDS2
BLOCKING
GPIO
sel_clk_fgpo_src
sel_clk_fgpo
clk_fgpo
BLOCKING
fgpo_output_enable_n
fgpo_output_select
invert_clk_fgpo
Figure 18: VDO_CLK2 Block Diagram
output router
VDO_CLK2
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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