PNX1502E Datasheet, PDF (670/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 23: LAN100 — Ethernet Media Access Controller
Table 1: LAN100 MMIO Register Map
Offset
Name
R/W
0x07 2230 PatternMatchMask0L R/W
0x07 2234 PatternMatchMask0H R/W
0x07 2238 PatternMatchCRC0 R/W
0x07 223C PatternMatchSkip0 R/W
0x07 2240 PatternMatchMask1L R/W
0x07 2244 PatternMatchMask1H R/W
0x07 2248 PatternMatchCRC1 R/W
0x07 224C PatternMatchSkip1 R/W
0x07 2250 PatternMatchMask2L R/W
0x07 2254 PatternMatchMask2H R/W
0x07 2258 PatternMatchCRC2 R/W
0x07 225C PatternMatchSkip2 R/W
0x07 2260 PatternMatchMask3L R/W
0x07 2264 PatternMatchMask3H R/W
0x07 2268 PatternMatchCRC3 R/W
0x07 226C PatternMatchSkip3 R/W
0x07 2270
to
0x07 2FDC
Standard Registers
0x07 2FE0 IntStatus
RO
0x07 2FE4 IntEnable
R/W
0x07 2FE8 IntClear
WO
0x07 2FEC IntSet
WO
0x07 2FF0
0x07 2FF4 PowerDown
R/W
0x07 2FF8
0x07 2FFC ModuleID
RO
Function
Bit 31:0 of Pattern Match 0
Bit 63:32 of Pattern Match 0
CRC Value for Pattern Match 0
Skip Bytes for Pattern Match 0
Bit 31:0 of Pattern Match 1
Bit 63:32 of Pattern Match 1
CRC Value for Pattern Match 1
Skip Bytes for Pattern Match 1
Bit 31:0 of Pattern Match 2
Bit 63:32 of Pattern Match 2
CRC Value for Pattern Match 2
Skip Bytes for Pattern Match 2
Bit 31:0 of Pattern Match 3
Bit 63:32 of Pattern Match 3
CRC Value for Pattern Match 3
Skip Bytes for Pattern Match 3
Reserved
Interrupt Status register
Interrupt Enable register
Interrupt Clear register
Interrupt Set register
Reserved
Power-down register
Reserved
Module ID
In QoS mode, that is, when the EnableQoS bit of the Command register is set, the
real-time transmit registers correspond to the registers of the low-priority transmit
channel and the non-real-time transmit registers correspond to the registers of the
high priority transmit channel.
3.2 Register Definitions
This section defines the bits of the individual LAN100 registers. The MII Interface
registers are mapped to addresses in the range 0x07 2000 – 0x07 20FC. For more
information about the MII Interface registers than is provided here, please refer to [2].
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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