PNX1502E Datasheet, PDF (178/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 5: The Clock Module
3.2 Registers Description
Table 11: CLOCK MODULE REGISTERS
Bit Symbol
Acces
s
Value
Description
PLL Registers
Offset 0x04,7000
PLL0_CTL
Reset values set for expected frequencies for faster boot-up, shorter boot code.
31:30 Reserved
R/W -
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
29 Turn Off Acknowledge R
-
Indicates that during a frequency change that the clock has been
driven low.
28 PLL Lock
R
-
A ‘1’ indicates that the PLL is locked
27:24 pll0_adj
R/W 0
Current adjustment. Section 2.2.1 on page 5-8.
23:21 Reserved
R/W -
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
20:12 pll0_n
R/W 0x4A
9-bit N parameter to PLL0
11:10 Reserved
R/W -
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
9:4 pll0_m
R/W 0x5
6-bit M parameter to PLL0. Section 2.2.1 on page 5-8.
3:2 pll0_p
R/W 0
2-bit P parameter to PLL0. Section 2.2.1 on page 5-8.
1
pll0_pd
R/W 0
1: powerdown PLL0
0
pll0_bp
R/W 1
0: Do not bypass the DDS
1: Bypass the DDS and use the xtal (27 MHz). Normal Operating
mode.
Offset 0x04,7004
PLL1_CTL
Reset values set for expected frequencies for faster boot-up, shorter boot code.
31:30 Reserved
R/W -
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
29 Turn Off Acknowledge R
-
Indicates that during a frequency change that the clock has been
driven low.
28 PLL Lock
R
-
A ‘1’ indicates that the PLL is locked
27:24 pll1_adj
R/W 4
Current adjustment. Section 2.2.1 on page 5-8.
23:21 Reserved
R/W -
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
20:12 pll1_n
R/W 0x22
9-bit N parameter to PLL1. Section 2.2.1 on page 5-8.
11:10 Reserved
R/W -
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
9:4 pll1_m
R/W 6
6-bit M parameter to PLL1. Section 2.2.1 on page 5-8.
3:2 pll1_p
R/W 2
2-bit P parameter to PLL1. Section 2.2.1 on page 5-8.
1
pll1_pd
R/W 0
1: powerdown PLL1
0
pll1_bp
R/W 1
0: Do not bypass the DDS.
1: Bypass the DDS and use the xtal (27 MHz)
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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