PNX1502E Datasheet, PDF (318/819 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX15xx Series
Chapter 9: DDR Controller
Table 4: Mapping scheme: 1024-Byte Interleaving, 256 Columns …Continued
MTL Address Range Row Address
Bank Address
Column Address
0x000:0800-0x000:081f 0x0000
0b10
0x0000-0x0007
0x000:0c00-0x000:0c1f 0x0000
0b11
0x0000-0x0007
0x000:1000-0x000:101f 0x0001
0b00
0x0000-0x0007
0x000:1400-0x000:141f 0x0001
0b01
0x0000-0x0007
0x000:2000-0x000:201f 0x0002
0b00
0x0000-0x0007
0x000:2400-0x000:241f 0x0002
0b01
0x0000-0x0007
Table 5: 1024-Byte Interleaving, 512 Columns
MTL Address Range Row Address
Bank Address
0x000:0000-0x000:001f 0x0000
0b00
0x000:0020-0x000:003f 0x0000
0b00
0x000:0040-0x000:005f 0x0000
0b00
0x000:0060-0x000:007f 0x0000
0b00
0x000:0400-0x000:041f 0x0000
0b00
0x000:0800-0x000:081f 0x0000
0b01
0x000:0c00-0x000:0c1f 0x0000
0b01
0x000:1000-0x000:101f 0x0000
0b10
0x000:1400-0x000:141f 0x0000
0b10
0x000:2000-0x000:201f 0x0001
0b00
0x000:2400-0x000:241f 0x0001
0b00
Column Address
0x0000-0x0007
0x0008-0x000f
0x0010-0x0017
0x0018-0x001f
0x0100-0x0107
0x0000-0x0007
0x0100-0x0107
0x0000-0x0007
0x0100-0x0107
0x0000-0x0007
0x0100-0x0107
2.3.2 DDR Memory Rank Locations
The DDR SDRAM Controller supports two DDR memory ranks. The location of these
two memory ranks in the MTL address space is defined by means of MMIO registers
RANK0_ADDR_LO, RANK0_ADDR_HI, and RANK1_ADDR_HI. Rank 1 starts where
rank0 leaves off in the MTL address space; i.e. the ranks are successive.
Programming of these MMIO registers should be consistent with the size of the
memories. An attempt to address an address outside of the two DDR memory ranks
will result in an error, which is registered by MMIO registers. Erroneous addressing
will still result in DDR read or write operations being performed.
Rank 1 starts where rank0 leaves off in the MTL address space i.e., the ranks are
successive. Programming these MMIO registers should be consistent with the
memory size. An attempt to address an address outside of the two DDR memory
ranks will result in an error, which is registered by MMIO registers. Erroneous
addressing will still result in DDR read or write operations being performed.
The start addresses of the ranks should be a multiple of the respective rank sizes.
The following examples will illustrate rank addressing and error detection situations.
12NC 9397 750 14321
Product data sheet
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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